Increased downscaling of CMOS circuits with respect to feature size and threshold voltage has a result of dramatically increasing in leakage current. So, leakage power reduction is an important design issue for active and standby modes as long as the technology scaling increased. In this paper, a simultaneous active and standby energy optimization methodology is proposed for 22 nm sub-threshold CMOS circuits. In the first phase, we investigate the dual threshold voltage design for active energy per cycle minimization. A slack based genetic algorithm is proposed to find the optimal reverse body bias assignment to set of noncritical paths gates to ensure low active energy per cycle with the maximum allowable frequency at the optimal supply vo

Experience the Islamic financial industry faces many challenges, most notably the lack of proper risk management tools that meet the requirements of legality and economic efficiency advantage from another side, so it requires the search for innovative ways to manage the risk of Islamic banking, Islamic finance industry is manufacture up-to-date, if compared with the financial industry (traditional), which increases the problematic of risk management in the Islamic financial industry nature of treatment which should be compatible with Islamic law, as well as economic efficiency, thereby Progress came the importance of research to highlight the entrance to Islamic financial engineering and the goals sought to be achieved through the use of

The traditional technique of generating MPSK signals is basically to use IQ modulator that involves analog processing like multiplication and addition where inaccuracies may exist and would lead to imbalance problems that affects the output modulated signal and hence the overall performance of the system. In this paper, a simple method is presented for generating the MPSK using logic circuits that basically generated M-carrier signals each carrier of different equally spaced phase shift. Then these carriers are time multiplexed, according to the data symbols, into the output modulated signal.

To ensure that a software/hardware product is of sufficient quality and functionality, it is essential to conduct thorough testing and evaluations of the numerous individual software components that make up the application. Many different approaches exist for testing software, including combinatorial testing and covering arrays. Because of the difficulty of dealing with difficulties like a two-way combinatorial explosion, this brings up yet another problem: time. Using client-server architectures, this research introduces a parallel implementation of the TWGH algorithm. Many studies have been conducted to demonstrate the efficiency of this technique. The findings of this experiment were used to determine the increase in speed and co

Sub-threshold operation has received a lot of attention in limited performance applications.However, energy optimization of sub-threshold circuits should be performed with the concern of the performance limitation of such circuit. In this paper, a dual size design is proposed for energy minimization of sub-threshold CMOS circuits. The optimal downsizing factor is determined and assigned for some gates on the off-critical paths to minimize the energy at the maximum allowable performance. This assignment is performed using the proposed slack based genetic algorithm which is a heuristic-mixed evolutionary algorithm. Some gates are heuristically assigned to the original and the downsized design based on their slack time determined by static tim

Testing is a vital phase in software development, and having the right amount of test data is an important aspect in speeding up the process. As a result of the integrationist optimization challenge, extensive testing may not always be practicable. There is also a shortage of resources, expenses, and schedules that impede the testing process. One way to explain combinational testing (CT) is as a basic strategy for creating new test cases. CT has been discussed by several scholars while establishing alternative tactics depending on the interactions between parameters. Thus, an investigation into current CT methods was started in order to better understand their capabilities and limitations. In this study, 97 publications were evalua

Skills learning is considered as an important factor in learning any subject as well as mathematics . Mathematical skills have a number of steps that should be learned and understood faster and with more accuracy . The practical or applied skills are type of learning which includes educational preparation and hand on skills is acquired which conducted by organized educational institutions. The sample included (120) students (males and females) first year / dept.of electrical technigues . The mathematical skills are implemented to wire up the electrical circuts. Test is implemented with questions concerned with the skills .statistical operations were conducted as well as the validity and standard deviation for the test .The results showed

In this study, the feasibility of Forward–Reverse osmosis processes was investigated for treating the oily wastewater. The first stage was applied forward osmosis process to recover pure water from oily wastewater. Sodium chloride (NaCl) and magnesium chloride (MgCl2) salts were used as draw solutions and the membrane that was used in forward osmosis (FO) process was cellulose triacetate (CTA) membrane. The operating parameters studied were: draw solution concentrations (0.25 – 0.75 M), oil concentration in feed solution (FS) (100-1000 ppm), the temperature of FS and draw solution (DS) (30 - 45 °C), pH of FS (4-10) and the flow rate of both DS and FS (20 - 60 l/h). It was found that the water flux and oil concentration in FS increas

  Quantum gates which are represented by unitary matrices have potentials to implement the reversible logic circuits. M and M+ gates are two well-known quantum gates which are used to synthesize the reversible logic circuits. In this work, we have used behavioral description of these gates, instead of unitary matrix description, to synthesize reversible logic circuits. By this method, M and M+ gates are shown in the truth table form.