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FPGA Realization of Two-Dimensional Wavelet and Wavelet Packet Transform
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The Field Programmable Gate Array (FPGA) approach is the most recent category, which takes the place in the implementation of most of the Digital Signal Processing (DSP) applications. It had proved the capability to handle such problems and supports all the necessary needs like scalability, speed, size, cost, and efficiency.

In this paper a new proposed circuit design is implemented for the evaluation of the coefficients of the two-dimensional Wavelet Transform (WT) and Wavelet Packet Transform (WPT) using FPGA is provided.

In this implementation the evaluations of the WT & WPT coefficients are depending upon filter tree decomposition using the 2-D discrete convolution algorithm. This implementation was achieved using an FPGA Kit after building the logical circuits on the specified kit that uses the Spartan-IIE electronic library type implemented using the Xilinx Foundation Series 2.1I software.

 

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Publication Date
Sun Mar 30 2025
Journal Name
Samarra Journal Of Engineering Science And Research
Proposed low Xilinx FPGA power consumption for recursive NOMA applied in optical visible light communication
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Today the NOMA has exponential growth in the use of Optical Visible Light Communication (OVLC) due to good features such as high spectral efficiency, low BER, and flexibility. Moreover, it creates a huge demand for electronic devices with high-speed processing and data rates, which leads to more FPGA power consumption. Therefore; it is a big challenge for scientists and researchers today to recover this problem by reducing the FPGA power and size of the devices. The subject matter of this article is producing an algorithm model to reduce the power consumption of (Field Programmable Gate Array) FPGA used in the design of the Non-Orthogonal Multiple Access (NOMA) techniques applied in (OVLC) systems combined with a blue laser. However, The po

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Publication Date
Tue Apr 01 2014
Journal Name
Journal Of Economics And Administrative Sciences
Multi-dimensional poverty and sustainable human development in Iraq
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The problem of poverty and deprivation constitute a humanitarian tragedy and its continuation may threaten the political achievements reached by the State. Iraq, in particular, and although he is one of the very rich countries due to availability of huge economic wealth, poverty indicators are still high. In addition, the main factor in the decline in the standard of living due to the weakness of the government's performance in the delivery of public services of water, electricity and sanitation. Thus, the guide for human development has been addressed which express the achievements that the state can be achieved both on a physical level or on the human level, so in order to put appropriate strategies and policies aimed at elimin

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Publication Date
Tue Sep 27 2022
Journal Name
Journal Of Engineering Research And Sciences
Images Compression using Combined Scheme of Transform Coding
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Some problems want to be solved in image compression to make the process workable and more efficient. Much work had been done in the field of lossy image compression based on wavelet and Discrete Cosine Transform (DCT). In this paper, an efficient image compression scheme is proposed, based on a common encoding transform scheme; It consists of the following steps: 1) bi-orthogonal (tab 9/7) wavelet transform to split the image data into sub-bands, 2) DCT to de-correlate the data, 3) the combined transform stage's output is subjected to scalar quantization before being mapped to positive, 4) and LZW encoding to produce the compressed data. The peak signal-to-noise (PSNR), compression ratio (CR), and compression gain (CG) measures were used t

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Publication Date
Thu May 18 2023
Journal Name
Journal Of Engineering
Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.

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Publication Date
Sun Dec 01 2013
Journal Name
Diyala Journal Of Engineering Sciences
Design and Simulation of parallel CDMA System Based on 3D-Hadamard Transform
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Future wireless systems aim to provide higher transmission data rates, improved spectral efficiency and greater capacity. In this paper a spectral efficient two dimensional (2-D) parallel code division multiple access (CDMA) system is proposed for generating and transmitting (2-D CDMA) symbols through 2-D Inter-Symbol Interference (ISI) channel to increase the transmission speed. The 3D-Hadamard matrix is used to generate the 2-D spreading codes required to spread the two-dimensional data for each user row wise and column wise. The quadrature amplitude modulation (QAM) is used as a data mapping technique due to the increased spectral efficiency offered. The new structure simulated using MATLAB and a comparison of performance for ser

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Publication Date
Tue Jun 30 2015
Journal Name
Al-khwarizmi Engineering Journal
Multi-Focus Image Fusion Based on Pixel Significance Using Counterlet Transform
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Abstract

 The objective of image fusion is to merge multiple sources of images together in such a way that the final representation contains higher amount of useful information than any input one.. In this paper, a weighted average fusion method is proposed. It depends on using weights that are extracted from source images using counterlet transform. The extraction method is done by making the approximated transformed coefficients equal to zero, then taking the inverse counterlet transform to get the details of the images to be fused. The performance of the proposed algorithm has been verified on several grey scale and color test  images, and compared with some present methods.

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Publication Date
Sun Dec 20 2020
Journal Name
Journal Of Accounting And Financial Studies ( Jafs )
Proposition Framework to Application Kaizen Cost Technique of to realization Target Pricing: Practical Study in the Al-Muthanna Cement Company
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The study the problem emerged in the inability of local companies to enter the field of active competition with other companies operating in the same economic sector due to the high cost of their products, hence, the companies that want to apply this technique can effectively compete in order to achieve those objectives.

  So this study focused on the goal of reducing the cost of products by reducing the cost product to a minimum , as the study was based in its hypothesis on the ability of companies to application this technique which in turn leads to increased profits under conditions of normal working and the power available and their potential in improving the quality of its products, as well as the need for full coordina

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Publication Date
Sat Feb 09 2019
Journal Name
Journal Of The College Of Education For Women
Hybrid Transform Based Denoising with Block Thresholding
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A frequently used approach for denoising is the shrinkage of coefficients of the noisy signal representation in a transform domain. This paper proposes an algorithm based on hybrid transform (stationary wavelet transform proceeding by slantlet transform); The slantlet transform is applied to the approximation subband of the stationary wavelet transform. BlockShrink thresholding technique is applied to the hybrid transform coefficients. This technique can decide the optimal block size and thresholding for every wavelet subband by risk estimate (SURE). The proposed algorithm was executed by using MATLAB R2010aminimizing Stein’s unbiased with natural images contaminated by white Gaussian noise. Numerical results show that our algorithm co

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Publication Date
Fri Mar 01 2013
Journal Name
Journal Of Engineering
Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
...Show More Authors

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.

Publication Date
Mon Dec 04 2023
Journal Name
Aip Conf. Proc
Double LA-transform and their properties for solving partial differential equations
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