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joe-2075
Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.

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Publication Date
Fri Mar 01 2013
Journal Name
Journal Of Engineering
Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.

Publication Date
Mon Mar 08 2021
Journal Name
Journal Of Physics: Conference Series
Design and Implementation of a Moving Robot Equipped with an Arm and an FPGA to Deliver Objects between Two Positions
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Abstract<p>In this paper a system is designed and implemented using a Field Programmable Gate Array (FPGA) to move objects from a pick up location to a delivery location. This transportation of objects is done via a vehicle equipped with a robot arm and an FPGA. The path between the two locations is followed by recognizing a black line between them. The black line is sensed by Infrared sensors (IR) located on the front and on the back of the vehicle. The Robot was successfully implemented by programming the Field Programmable Gate Array with the designed system that was described as a state diagram and the robot operated properly.</p>
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Publication Date
Fri Jul 21 2023
Journal Name
Journal Of Engineering
Design and Implementation of a Multiplier free FPGA based OFDM Transmitter
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Orthogonal Frequency Division Multiplexing (OFDM) is an efficient multi-carrier technique.The core operation in the OFDM systems is the FFT/IFFT unit that requires a large amount of hardware resources and processing delay. The developments in implementation techniques likes Field Programmable Gate Array (FPGA) technologies have made OFDM a feasible option. The goal of this paper is to design and implement an OFDM transmitter based on Altera FPGA using Quartus software. The proposed transmitter is carried out to simplify the Fourier transform calculation by using decoder instead of multipliers. After programming ALTERA DE2 FPGA kit with implemented project, several practical tests have been done starting from monitoring all the results of

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Publication Date
Mon Jul 10 2023
Journal Name
Journal Of Engineering
Design and Implementation of Single-Phase Boost PFC Converter
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In this paper, a single-phase boost type ac-dc converter with power factor correction (PFC) technique is designed and implemented. A current mode control at a constant switching frequency is used as a control strategy for PFC converter. The PFC converter is a single-stage singleswitch boost converter that uses a current shaping technique to reshape the non-sinusoidal input current drawn by the bulky capacitor in the conventional rectifier. This technique should provide an input current with almost free-harmonics, comply with the IEC61000-3-2 limits, and a system operates with near unity power factor. The other function of the boost converter that should be
accomplished is to provide a regulated DC output voltage. The complete designed

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Publication Date
Mon Jul 31 2017
Journal Name
Journal Of Engineering
Development of an On-Line Self-Tuning FPGA-PID-PWM Control Algorithm Design for DC-DC Buck Converter in Mobile Applications
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Publication Date
Tue Dec 13 2022
Journal Name
Lecture Notes In Networks And Systems
Design and FPGA Implementation of Matrix Multiplier Using DEMUX-RCA-Based Vedic Multiplier
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Publication Date
Sun Apr 30 2017
Journal Name
Journal Of Engineering
Implementation of a Proposed Load-Shedding System Using Altera DE2 FPGA
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A load-shedding controller suitable for small to medium size loads is designed and implemented based on preprogrammed priorities and power consumption for individual loads. The main controller decides if a particular load can be switched ON or not according to the amount of available power generation, load consumption and loads priorities. When themaximum allowed power consumption is reached and the user want to deliver power to additional load, the controller will decide if this particular load should be denied receiving power if its priority is low. Otherwise, it can be granted to receive power if its priority is high and in this case lower priority loads are automatically switched OFF in order not to overload the power generation. The

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Publication Date
Sun Feb 10 2019
Journal Name
Journal Of The College Of Education For Women
DESIGN AND IMPLEMENTATION AN IRAQI CITIES DATABASE USING K-D TREE
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This research include design and implementation of an Iraqi cities database using spatial data structure for storing data in two or more dimension called k-d tree .The proposed system should allow records to be inserted, deleted and searched by name or coordinate. All the programming of the proposed system written using Delphi ver. 7 and performed on personal computer (Intel core i3).

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Publication Date
Wed Apr 01 2015
Journal Name
Journal Of Engineering
Software Implementation of Binary BCH Decoder Using Microcontroller
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In this paper a decoder of binary BCH code is implemented using a PIC microcontroller for code length n=127 bits with multiple error correction capability, the results are presented for correcting errors up to 13 errors. The Berkelam-Massey decoding algorithm was chosen for its efficiency. The microcontroller PIC18f45k22 was chosen for the implementation and programmed using assembly language to achieve highest performance. This makes the BCH decoder implementable as a low cost module that can be used as a part of larger systems. The performance evaluation is presented in terms of total number of instructions and the bit rate.

 

 

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Publication Date
Wed Jul 01 2020
Journal Name
Journal Of Engineering
Bat Algorithm Based an Adaptive PID Controller Design for Buck Converter Model
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The aim of this paper is to design a PID controller based on an on-line tuning bat optimization algorithm for the step-down DC/DC buck converter system which is used in the battery operation of the mobile applications. In this paper, the bat optimization algorithm has been utilized to obtain the optimal parameters of the PID controller as a simple and fast on-line tuning technique to get the best control action for the system. The simulation results using (Matlab Package) show the robustness and the effectiveness of the proposed control system in terms of obtaining a suitable voltage control action as a smooth and unsaturated state of the buck converter input voltage of ( ) volt that will stabilize the buck converter sys

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