Quantitative analysis of human voice has been subject of interest and the subject gained momentum when human voice was identified as a modality for human authentication and identification. The main organ responsible for production of sound is larynx and the structure of larynx along with its physical properties and modes of vibration determine the nature and quality of sound produced. There has been lot of work from the point of view of fundamental frequency of sound and its characteristics. With the introduction of additional applications of human voice interest grew in other characteristics of sound and possibility of extracting useful features from human voice. We conducted a study using Fast Fourier Transform (FFT) technique to analy

In this paper, a FPGA model of intelligent traffic light system with power saving was built. The intelligent traffic light system consists of sensors placed on the side's ends of the intersection to sense the presence or absence of vehicles. This system reduces the waiting time when the traffic light is red, through the transition from traffic light state to the other state, when the first state spends a lot of time, because there are no more vehicles. The proposed system is built using VHDL, simulated using Xilinx ISE 9.2i package, and implemented using Spartan-3A XC3S700A FPGA kit. Implementation and Simulation behavioral model results show that the proposed intelligent traffic light system model satisfies the specified operational req

Compressing the speech reduces the data storage requirements, leading to reducing the time of transmitting the digitized speech over long-haul links like internet. To obtain best performance in speech compression, wavelet transforms require filters that combine a number of desirable properties, such as orthogonality and symmetry.The MCT bases functions are derived from GHM bases function using 2D linear convolution .The fast computation algorithm methods introduced here added desirable features to the current transform. We further assess the performance of the MCT in speech compression application. This paper discusses the effect of using DWT and MCT (one and two dimension) on speech compression. DWT and MCT performances in terms of comp

Future wireless communication systems must be able to accommodate a large number of users and simultaneously to provide the high data rates at the required quality of service. In this paper a method is proposed to perform the N-Discrete Hartley Transform (N-DHT) mapper, which are equivalent to 4-Quadrature Amplitude Modulation (QAM), 16-QAM, 64-QAM, 256-QAM, … etc. in spectral efficiency. The N-DHT mapper is chosen in the Multi Carrier Code Division Multiple Access (MC-CDMA) structure to serve as a data mapper instead of the conventional data mapping techniques like QPSK and QAM schemes. The proposed system is simulated using MATLAB and compared with conventional MC-CDMA for Additive White Gaussian Noise, flat, and multi-path selective fa

The present work provides theoretical investigation of laser photoacoustic one dimensional imaging to detect a blood vessel or tumor embedded within normal tissue. The key task in photoacoustic imaging is to have acoustic signal that help to determine the size and location of the target object inside normal tissue. The analytical simulation used a spherical wave model representing target object (blood vessel or tumor) inside normal tissue. A computer program in MATLAB environment has been written to realize this simulation. This model generates time resolved acoustic wave signal that include both expansion and contraction parts of the wave. The photoacoustic signal from the target object is simulated for a range of laser pulse duration 1

Today the NOMA has exponential growth in the use of Optical Visible Light Communication (OVLC) due to good features such as high spectral efficiency, low BER, and flexibility. Moreover, it creates a huge demand for electronic devices with high-speed processing and data rates, which leads to more FPGA power consumption. Therefore; it is a big challenge for scientists and researchers today to recover this problem by reducing the FPGA power and size of the devices. The subject matter of this article is producing an algorithm model to reduce the power consumption of (Field Programmable Gate Array) FPGA used in the design of the Non-Orthogonal Multiple Access (NOMA) techniques applied in (OVLC) systems combined with a blue laser. However, The po

Steganography is a mean of hiding information within a more obvious form of
communication. It exploits the use of host data to hide a piece of information in such a way
that it is imperceptible to human observer. The major goals of effective Steganography are
High Embedding Capacity, Imperceptibility and Robustness. This paper introduces a scheme
for hiding secret images that could be as much as 25% of the host image data. The proposed
algorithm uses orthogonal discrete cosine transform for host image. A scaling factor (a) in
frequency domain controls the quality of the stego images. Experimented results of secret
image recovery after applying JPEG coding to the stego-images are included.

Digital image is widely used in computer applications. This paper introduces a proposed method of image zooming based upon inverse slantlet transform and image scaling. Slantlet transform (SLT) is based on the principle of designing different filters for different scales.

      First we apply SLT on color image, the idea of transform color image into slant, where large coefficients are mainly the   signal and smaller one represent the noise. By suitably modifying these coefficients , using scaling up image by  box and Bartlett filters so that the image scales up to 2X2 and then inverse slantlet transform from modifying coefficients using to the reconstructed image .

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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.