It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.
The Frequency-hopping Spread Spectrum (FHSS) systems and techniques are using in military and civilianradar recently and in the communication system for securing the information on wireless communications link channels, for example in the Wi-Fi 8.02.X IEEE using multiple number bandwidth and frequencies in the wireless channel in order to hopping on them for increasing the security level during the broadcast, but nowadays FHSS problem, which is, any Smart Software Defined Radio (S-SDR) can easily detect a wireless signal at the transmitter and the receiver for the hopping sequence in both of these, then duplicate this sequence in order to hack the signal on both transmitter and receiver messages using the order of the se
... Show MoreBall and Plate (B&P) system is a benchmark system in the control engineering field that has been used to verify many control methods. In this paper the design of a sliding mode . controller has been investigated and verified in real-time via implementation on a real ball and plate system hardware. The mathematical model has been derived and the necessary parameters have been measured. The sliding mode controller has been designed based on the obtained mathematical model. The resulting controller has been implemented using the Arduino Mega 2560 and a ball and plate system built completely from scratch. The Arduino has been programmed by the Arduino support target for Simulink. Three test signals has been used for verification purposes
... Show MoreThis research involves design and simulation of GaussianFSK transmitter in UHF band using direct modulation of ΣΔ fractional-N synthesizer with the following specifications:
Frequency range (869.9– 900.4) MHz, data rate 150kbps, channel spacing (500 kHz), Switching time 1 µs, & phase noise @10 kHz = -85dBc.
New circuit techniques have been sought to allow increased integration of radio transmitters and receivers, along with new radio architectures that take advantage of such techniques. Characteristics such as low power operation, small size, and low cost have become the dominant design criteria by which these systems are judged.
A direct modulation by ΣΔ fractional-N synthesizer is proposed
... Show MoreLet R be a 2-torision free prime ring and ?, ?? Aut(R). Furthermore, G: R×R?R is a symmetric generalized (?, ?)-Biderivation associated with a nonzero (?, ?)-Biderivation D. In this paper some certain identities are presented satisfying by the traces of G and D on an ideal of R which forces R to be commutative
This research describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc
The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar & reference divider in single chip. Therefore our system consists of a single chip contains (low phase noise PFD, charge pump, prescalar & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip
... Show MoreA tunable band pass filter based on fiber Bragg grating sensor using an in-fiber Mach-Zender interferometer with dual micro-cavities is presented. The micro-cavity was formed by splicing together a conventional single-mode fiber and a solid core photonic crystal fiber (SCPCF) with simple arc discharge technique. Different parameters such as arc power, length of the SCPCF and the overlap gap between samples were considered to control the fabrication process. The ellipsoidal air-cavity between the two fibers forms Fabry-Perot cavity. The diffraction loss was very low due to short cavity length. Ellipsoidal shape micro-cavities were experimentally achieved parallel to the propagation axis having dimensions of (24.92 – 62.32) μm of width
... Show MoreThis paper investigate a sensorless speed control of a separately excited dc motor fed from a buck type dc-dc converter. The control system is designed in digital technique by using a two dimension look-up table. The performance of the drive system was evaluated by digital simulation using Simulink toolbox of Matlab.
Accurate predictive tools for VLE calculation are always needed. A new method is introduced for VLE calculation which is very simple to apply with very good results compared with previously used methods. It does not need any physical property except each binary system need tow constants only. Also, this method can be applied to calculate VLE data for any binary system at any polarity or from any group family. But the system binary should not confirm an azeotrope. This new method is expanding in application to cover a range of temperature. This expansion does not need anything except the application of the new proposed form with the system of two constants. This method with its development is applied to 56 binary mixtures with 1120 equili
... Show MoreThe Field Programmable Gate Array (FPGA) approach is the most recent category, which takes the place in the implementation of most of the Digital Signal Processing (DSP) applications. It had proved the capability to handle such problems and supports all the necessary needs like scalability, speed, size, cost, and efficiency.
In this paper a new proposed circuit design is implemented for the evaluation of the coefficients of the two-dimensional Wavelet Transform (WT) and Wavelet Packet Transform (WPT) using FPGA is provided.
In this implementation the evaluations of the WT & WPT coefficients are depending upon filter tree decomposition using the 2-D discrete convolution algorithm. This implementation w
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