A tunable band pass filter based on fiber Bragg grating sensor using an in-fiber Mach-Zender interferometer with dual micro-cavities is presented. The micro-cavity was formed by splicing together a conventional single-mode fiber and a solid core photonic crystal fiber (SCPCF) with simple arc discharge technique. Different parameters such as arc power, length of the SCPCF and the overlap gap between samples were considered to control the fabrication process. The ellipsoidal air-cavity between the two fibers forms Fabry-Perot cavity. The diffraction loss was very low due to short cavity length. Ellipsoidal shape micro-cavities were experimentally achieved parallel to the propagation axis having dimensions of (24.92 – 62.32) μm of width and (3.82 – 18.2) μm of length. The maximum tunability 0.73nm was achieved at minimum length of (SCPCF) in the range (1545.673-1545.546) nm. A micro- cavity with width and length as high as 62.32 um and 18.3 um have higher sensitivity 0.31 nm/cm than temperature sensitivities of 18 pm/°C.
In this research, optical communication coding systems are designed and constructed by utilizing Frequency Shift Code (FSC) technique. Calculations of the system quality represented by signal to noise ratio (S/N), Bit Error Rate (BER),and Power budget are done. In FSC system, the data of Nonreturn- to–zero (NRZ ) with bit rate at 190 kb/s was entered into FSC encoder circuit in transmitter unit. This data modulates the laser source HFCT-5205 with wavelength at 1310 nm by Intensity Modulation (IM) method, then this data is transferred through Single Mode (SM) optical fiber. The recovery of the NRZ is achieved using decoder circuit in receiver unit. The calculations of BER and S/N for FSC system a
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Ball and Plate (B&P) system is a benchmark system in the control engineering field that has been used to verify many control methods. In this paper the design of a sliding mode . controller has been investigated and verified in real-time via implementation on a real ball and plate system hardware. The mathematical model has been derived and the necessary parameters have been measured. The sliding mode controller has been designed based on the obtained mathematical model. The resulting controller has been implemented using the Arduino Mega 2560 and a ball and plate system built completely from scratch. The Arduino has been programmed by the Arduino support target for Simulink. Three test signals has been used for verification purposes
... Show MoreThe quality of Global Navigation Satellite Systems (GNSS) networks are considerably influenced by the configuration of the observed baselines. Where, this study aims to find an optimal configuration for GNSS baselines in terms of the number and distribution of baselines to improve the quality criteria of the GNSS networks. First order design problem (FOD) was applied in this research to optimize GNSS network baselines configuration, and based on sequential adjustment method to solve its objective functions.
FOD for optimum precision (FOD-p) was the proposed model which based on the design criteria of A-optimality and E-optimality. These design criteria were selected as objective functions of precision, whic
... Show More The vast majority of EC applications are the web-based deployed in 3-tire Server-Client environment, the data within such application often resides within several heterogeneous data sources. Building a single application that can access each data sources can be a matter of challenging; this paper concerns with developing a software program that runs transparently against heterogeneous environment for an EC-application.
Developing and researching antenna designs are analogous to excavating in an undiscovered mine. This paper proposes a multi-band antenna with a new hexagonal ring shape, theoretically designed, developed, and analyzed using a CST before being manufactured. The antenna has undergone six changes to provide the best performance. The results of the surface current distribution and the electric field distribution on the surface of the hexagonal patch were theoretically analyzed and studied. The sequential approach taken to determine the most effective design is logical, and prevents deviation from the work direction. After comparing the six theoretical results, the fifth model proved to be the best for making a prototype. Measured results rep
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This research describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc
The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar & reference divider in single chip. Therefore our system consists of a single chip contains (low phase noise PFD, charge pump, prescalar & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip
... Show MoreA compact microstrip six-port reflectometer (SPR) with extended bandwidth is proposed in this paper. The design is based on using 16-dB multi-section coupled line directional couplers and a multi-section 3-dB Wilkinson power divider operating from 1 to 6 GHz. The proposed SPR employs only two calibration standards: a matched load and an open load. As compared to other dielectric substrates, fabricating the proposed SPR involves using a low-cost (FR4) substrate. A novel algorithm is also proposed to estimate the complex reflection coefficient over the frequency ranges at which the standard performance of the circuit components is not fully satisfied. The new algorithm is based on the circles’ intersection points, which have been de
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.
This paper describes the digital chaotic signal with ship map design. The robust digital implementation eliminates the variation tolerance and electronics noise problems common in analog chaotic circuits. Generation of good non-repeatable and nonpredictable random sequences is of increasing importance in security applications. The use of 1-D chaotic signal to mask useful information and to mask it unrecognizable by the receiver is a field of research in full expansion. The piece-wise 1-D map such as ship map is used for this paper. The main advantages of chaos are the increased security of the transmission and ease of generation of a great number of distinct sequences. As consequence, the number of users in the systems can be increased. Rec
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