Variable-Length Subnet Masks (VLSM), often referred to as "subnetting a subnet", is used to maximize addressing efficiency. The network administrator is able to use a long mask on networks with few hosts, and a short mask on subnets with many hosts. This addressing scheme allows growth and does not involve wasting addresses. VLSM gives a way of subnetting a network with minimal loses of IP addresses for a specific range. Unfortunately, the network administrator has to perform several mathematical steps (or use charts) to get the required results from VLSM. In this paper, a simple graph simulator is proposed (using Visual Basic 6.0 Language) to perform all the required mathematical steps and to display the obtained required information (the subnet ID, broadcast ID, usable addresses for sub networks and others). The simulator also includes the ability to draw a suggested network topology that matches the entries. The implementation of the simulation required only very few entries (IP, prefix and number of subnets).This simulator is useful for students, instructors, and network engineers to analysis and design a VLSM network by providing all required information in simple, fast and easy steps. Moreover, the software draws a full detailed suggested network topology which is considered a helpful tool for the network administrator that he should have.
Single-photon detection concept is the most crucial factor that determines the performance of quantum key distribution (QKD) systems. In this paper, a simulator with time domain visualizers and configurable parameters using continuous time simulation approach is presented for modeling and investigating the performance of single-photon detectors operating in Gieger mode at the wavelength of 830 nm. The widely used C30921S silicon avalanche photodiode was modeled in terms of avalanche pulse, the effect of experiment conditions such as excess voltage, temperature and average photon number on the photon detection efficiency, dark count rate and afterpulse probability. This work shows a general repeatable modeling process for significant perform
... Show More
It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.
In this research, optical communication coding systems are designed and constructed by utilizing Frequency Shift Code (FSC) technique. Calculations of the system quality represented by signal to noise ratio (S/N), Bit Error Rate (BER),and Power budget are done. In FSC system, the data of Nonreturn- to–zero (NRZ ) with bit rate at 190 kb/s was entered into FSC encoder circuit in transmitter unit. This data modulates the laser source HFCT-5205 with wavelength at 1310 nm by Intensity Modulation (IM) method, then this data is transferred through Single Mode (SM) optical fiber. The recovery of the NRZ is achieved using decoder circuit in receiver unit. The calculations of BER and S/N for FSC system a
... Show More
(13)
(15)
The current research aims to develop the skills of the kindergarten students in designing and implementing a theater for gauntlets made of cardboard materials. To study this, the researcher determined to build teaching plans for design and implementation skills according to (Kolb model).
The results of this research showed the effectiveness of teaching plans according to (Kolb's model) in developing skills of design and implementation (theater for gauntlets made of cardboard materials) for the students of the Kindergarten Department - the experimental group. Which had a positive effect to reach the desired results in the design and implementation of the gauntlet theater and dealing with cardboard materials
It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.
Car drivers hear many kinds of noise inside their vehicles' cabins, and the most annoying ones are the noise generated by tires, engines, and outside winds. Noise affects the comfort of the passengers inside the cabin, and it’s sad to say that modern cars are noisier in many kinds of noise signals due to using a lot of plastic materials in new budget cars. For expensive and luxury cars, the problem is solved by using better sound insulation materials, but for the budget ones, the approach used here is effective. It is called Active Noise Cancellation and can be done using analog or digital electronics. An operational amplifier and filters are used for the analog one, and in the digital one, signal processor chips are used. In engineeri
... Show More
Under aerobic and anaerobic conditions, two laboratory-scale reactors were operated. Each reactor
was packed with 8.5 kg of shredded synthetic solid waste (less than 5 cm) that was prepared according to an
average composition of domestic solid waste in the city of Kirkuk. Using an air compressor, aerobic
conditions were created in the aerobic reactor. This study shows that the aerobic reactor was more efficient in
COD and BOD5 removal which were 97.88% and 91.25% while in case of anaerobic reactor, they were
66.53%and 19.11%, respectively.