Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number o

  The search is an application for one of the problems of mathematics in the computer; as providing construction and design of a major program to calculate the inverse permutations of the symmetric group Sn , where 1 ≤ n ≤ 13; using some of the methods used in the Number Theory by computer . Also the research includes design flow chart for the main program and design flow chart for the program inverse permutations and we give some illustrative examples for different symmetric groups and their inverse permutations.

 A particle swarm optimization algorithm and neural network like self-tuning PID controller for CSTR system is presented. The scheme of the discrete-time PID control structure is based on neural network and tuned the parameters of the PID controller by using a particle swarm optimization PSO technique as a simple and fast training algorithm. The proposed method has advantage that it is not necessary to use a combined structure of identification and decision because it used PSO. Simulation results show the effectiveness of the proposed adaptive PID neural control algorithm in terms of minimum tracking error and smoothness control signal obtained for non-linear dynamical CSTR system.

  This paper deals with proposing new lifting scheme (HYBRID Algorithm) that is capable of preventing images and documents which are fraud through decomposing there in to the real colors value arrays (red, blue and green) to create retrieval keys for its properties and store it in the database and then check the document originality by retrieve the query image or document through the decomposition described above and compare the predicted color values (retrieval keys)  of the query document with those stored in the database. The proposed algorithm has been developed from the two known lifting schemes (Haar and D4) by merging them to find out HYBRID lifting scheme. The validity and accuracy of the proposed algorithm have been ev

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.

This paper proposes an on-line adaptive digital Proportional Integral Derivative (PID) control algorithm based on Field Programmable Gate Array (FPGA) for Proton Exchange Membrane Fuel Cell (PEMFC) Model. This research aims to design and implement Neural Network like a digital PID using FPGA in order to generate the best value of the hydrogen partial pressure action (PH₂) to control the stack terminal output voltage of the (PEMFC) model during a variable load current applied. The on-line Particle Swarm Optimization (PSO) algorithm is used for finding and tuning the optimal value of the digital PID-NN controller (kp, ki, and kd) parameters that improve the dynamic behavior of the closed-loop digital control fue

In this work, the performance of the receiver in a quantum cryptography system based on BB84 protocol is scaled by calculating the Quantum Bit Error Rate (QBER) of the receiver. To apply this performance test, an optical setup was arranged and a circuit was designed and implemented to calculate the QBER. This electronic circuit is used to calculate the number of counts per second generated by the avalanche photodiodes set in the receiver. The calculated counts per second are used to calculate the QBER for the receiver that gives an indication for the performance of the receiver. Minimum QBER, 6%, was obtained with avalanche photodiode excess voltage equals to 2V and laser diode power of 3.16 nW at avalanche photodiode temperature of -10

Background and Aim: due to the rapid growth of data communication and multimedia system applications, security becomes a critical issue in the communication and storage of images. This study aims to improve encryption and decryption for various types of images by decreasing time consumption and strengthening security. Methodology: An algorithm is proposed for encrypting images based on the Carlisle Adams and Stafford Tavares CAST block cipher algorithm with 3D and 2D logistic maps. A chaotic function that increases the randomness in the encrypted data and images, thereby breaking the relation sequence through the encryption procedure, is introduced. The time is decreased by using three secure and private S-Boxes rather than using si