Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost.
إنّ التّأمّل في الدّراسات الأدبيّة النّقديّة الحديثة الّتي تنظر إلى النّصّ أنّه لوحة تتشكّل من مجموعة تداخلات نصّيّة سابقة للنصّ المُنتج أو مُعاصرة له، تدفع القارئ إلى الغوص في أعماق النّصوص وتحليلها والكشف عن الآليّات والإجراءات الّتي اعتمدت في إنتاجه، وإظهار الجماليّات الفنّيّة التي شكلت في مُجملها كائنا حيّا يُعبّر عن حالات إنسانيّة مُستمرة الحدوث رغم تقادم الأزمان.
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