Ball and Plate (B&P) system is a benchmark system in the control engineering field that has been used to verify many control methods. In this paper the design of a sliding mode . controller has been investigated and verified in real-time via implementation on a real ball and plate system hardware. The mathematical model has been derived and the necessary parameters have been measured. The sliding mode controller has been designed based on the obtained mathematical model. The resulting controller has been implemented using the Arduino Mega 2560 and a ball and plate system built completely from scratch. The Arduino has been programmed by the Arduino support target for Simulink. Three test signals has been used for verification purposes

Sewer network is one of the important utilities in modern cities which discharge the sewage from all facilities. The increase of population numbers consequently leads to the increase in water consumption; hence waste water generation. Sewer networks work is very expensive and need to be designed accurately. Thus construction effective sewer network system with minimum cost is very necessary to handle waste water generation.

 In this study trunk mains networks design was applied which connect the pump stations together by underground pipes for too long distances. They usually have large diameters with varying depths which consequently need excavations and gathering from pump stations and transport the sewage

The Backstepping Sliding Mode Control is a control technique used for controlling nonlinear systems. In this paper, the performance of the backstepping sliding mode controller schemes for the angular velocity control for a rotary actuator of an angular velocity control system that utilizes a novel hydraulic flow control method called inlet throttling was investigated. For the angular velocity dynamic, a linear state feedback with suitable high gain is designed as the virtual controller, where steady state error can be made arbitrarily small according to the gain value. A time varying sliding variable is then selected based on the designed virtual controller. The resulting control design is robust, and the maximum error of the angular veloci

T-joints are common structures encountered in the assemblage of many industrial applications due to their advantages. However, joining these structures when using Friction Stir Welding (FSW) could be prone to defects that cause severe consequences like loss of strength and fracture. The current paper implements an experimental procedure to assess the effect of geometrical tool shape on void formation in friction stir welded AA 6061-T6 T-joint configuration. Taguchi optimization method was put into service to minimize the number of experiments and fulfil the goal of discovering the optimal FSW parameters that allow the manufacturing of such configurations with high mechanical properties. X-ray radiography and micrograph images were u

This research  describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc

  The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar &  reference divider in single chip. Therefore our system consists of  a single chip contains (low phase noise PFD, charge pump, prescalar  & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.

In this research, optical communication coding systems are designed and constructed by utilizing Frequency Shift Code (FSC) technique. Calculations of the system quality represented by signal to noise ratio (S/N), Bit Error Rate (BER),and Power budget are done. In FSC system, the data of Nonreturn- to–zero (NRZ ) with bit rate at 190 kb/s was entered into FSC encoder circuit in transmitter unit. This data modulates the laser source HFCT-5205 with wavelength at 1310 nm by Intensity Modulation (IM) method, then this data is transferred through Single Mode (SM) optical fiber. The recovery of the NRZ is achieved using decoder circuit in receiver unit. The calculations of BER and S/N for FSC system a