Sewer network is one of the important utilities in modern cities which discharge the sewage from all facilities. The increase of population numbers consequently leads to the increase in water consumption; hence waste water generation. Sewer networks work is very expensive and need to be designed accurately. Thus construction effective sewer network system with minimum cost is very necessary to handle waste water generation.

 In this study trunk mains networks design was applied which connect the pump stations together by underground pipes for too long distances. They usually have large diameters with varying depths which consequently need excavations and gathering from pump stations and transport the sewage

Cloud computing provides huge amount of area for storage of the data, but with an increase of number of users and size of their data, cloud storage environment faces earnest problem such as saving storage space, managing this large data, security and privacy of data. To save space in cloud storage one of the important methods is data deduplication, it is one of the compression technique that allows only one copy of the data to be saved and eliminate the extra copies. To offer security and privacy of the sensitive data while supporting the deduplication, In this work attacks that exploit the hybrid cloud deduplication have been identified, allowing an attacker to gain access to the files of other users based on very small hash signatures of

This research include design and implementation of an Iraqi cities database using spatial data structure for storing data in two or more dimension called k-d tree .The proposed system should allow records to be inserted, deleted and searched by name or coordinate. All the programming of the proposed system written using Delphi ver. 7 and performed on personal computer (Intel core i3).

This paper proposes a collaborative system called Recycle Rewarding System (RRS), and focuses on the aspect of using information communication technology (ICT) as a tool to promote greening. The idea behind RRS is to encourage recycling collectors by paying them for earning points. In doing so, both the industries and individuals reap the economical benefits of such system. Finally, and more importantly, the system intends to achieve a green environment for the Earth. This paper discusses the design and implementation of the RRS, involves: the architectural design, selection of components, and implementation issues. Five modules are used to construct the system, namely: database, data entry, points collecting and recording, points reward

Ball and Plate (B&P) system is a benchmark system in the control engineering field that has been used to verify many control methods. In this paper the design of a sliding mode . controller has been investigated and verified in real-time via implementation on a real ball and plate system hardware. The mathematical model has been derived and the necessary parameters have been measured. The sliding mode controller has been designed based on the obtained mathematical model. The resulting controller has been implemented using the Arduino Mega 2560 and a ball and plate system built completely from scratch. The Arduino has been programmed by the Arduino support target for Simulink. Three test signals has been used for verification purposes

This research  describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc

  The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar &  reference divider in single chip. Therefore our system consists of  a single chip contains (low phase noise PFD, charge pump, prescalar  & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.