With the continuous downscaling of semiconductor processes, the growing power density and thermal issues in multicore processors become more and more challenging, thus reliable dynamic thermal management (DTM) is required to prevent severe challenges in system performance. The accuracy of the thermal profile, delivered to the DTM manager, plays a critical role in the efficiency and reliability of DTM, different sources of noise and variations in deep submicron (DSM) technologies severely affecting the thermal data that can lead to significant degradation of DTM performance. In this article, we propose a novel fault-tolerance scheme exploiting approximate computing to mitigate the DSM effects on DTM efficiency. Approximate computing in hardware design can lead to significant gains in energy efficiency, area, and performance. To exploit this opportunity, there is a need for design abstractions that can systematically incorporate approximation in hardware design which is the main contribution of our work. Our proposed scheme achieves 11.20% lower power consumption, 6.59% smaller area, and 12% reduction in the number of wires, while increasing DTM efficiency by 5.24%.
Receipt date:12/7/2020 accepted date:24/1/2021 Publication date:31/12/2021
This work is licensed under a Creative Commons Attribution 4.0 International License.
The constant characteristic of international relations is the constant change due to political, economic and military developments in addition to technology, and this in turn has led to many transformations in the concept of power, its uses, and the elements that form power and its distribution, and according to those variables, the concept of power has shifted from hard to soft, up to smart powe
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The first successful implementation of Artificial Neural Networks (ANNs) was published a little over a decade ago. It is time to review the progress that has been made in this research area. This paper provides taxonomy for classifying Field Programmable Gate Arrays (FPGAs) implementation of ANNs. Different implementation techniques and design issues are discussed, such as obtaining a suitable activation function and numerical truncation technique trade-off, the improvement of the learning algorithm to reduce the cost of neuron and in result the total cost and the total speed of the complete ANN. Finally, the implementation of a complete very fast circuit for the pattern of English Digit Numbers NN has four layers of 70 nodes (neurons) o
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