Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number of wires. In addition, it has small penalty on the network performance, represented by the average latency and comparable codec area overhead to other schemes.
Information security in data storage and transmission is increasingly important. On the other hand, images are used in many procedures. Therefore, preventing unauthorized access to image data is crucial by encrypting images to protect sensitive data or privacy. The methods and algorithms for masking or encoding images vary from simple spatial-domain methods to frequency-domain methods, which are the most complex and reliable. In this paper, a new cryptographic system based on the random key generator hybridization methodology by taking advantage of the properties of Discrete Cosine Transform (DCT) to generate an indefinite set of random keys and taking advantage of the low-frequency region coefficients after the DCT stage to pass them to
... Show MoreThe Field Programmable Gate Array (FPGA) approach is the most recent category, which takes the place in the implementation of most of the Digital Signal Processing (DSP) applications. It had proved the capability to handle such problems and supports all the necessary needs like scalability, speed, size, cost, and efficiency.
In this paper a new proposed circuit design is implemented for the evaluation of the coefficients of the two-dimensional Wavelet Transform (WT) and Wavelet Packet Transform (WPT) using FPGA is provided.
In this implementation the evaluations of the WT & WPT coefficients are depending upon filter tree decomposition using the 2-D discrete convolution algorithm. This implementation w
... Show MoreIn this paper, our aim is to study variational formulation and solutions of 2-dimensional integrodifferential equations of fractional order. We will give a summery of representation to the variational formulation of linear nonhomogenous 2-dimensional Volterra integro-differential equations of the second kind with fractional order. An example will be discussed and solved by using the MathCAD software package when it is needed.
This paper proposes an on-line adaptive digital Proportional Integral Derivative (PID) control algorithm based on Field Programmable Gate Array (FPGA) for Proton Exchange Membrane Fuel Cell (PEMFC) Model. This research aims to design and implement Neural Network like a digital PID using FPGA in order to generate the best value of the hydrogen partial pressure action (PH2) to control the stack terminal output voltage of the (PEMFC) model during a variable load current applied. The on-line Particle Swarm Optimization (PSO) algorithm is used for finding and tuning the optimal value of the digital PID-NN controller (kp, ki, and kd) parameters that improve the dynamic behavior of the closed-loop digital control fue
... Show MoreThis paper presents a new design of a nonlinear multi-input multi-output PID neural controller of the active brake steering force and the active front steering angle for a 2-DOF vehicle model based on modified Elman recurrent neural. The goal of this work is to achieve the stability and to improve the vehicle dynamic’s performance through achieving the desired yaw rate and reducing the lateral velocity of the vehicle in a minimum time period for preventing the vehicle from slipping out the road curvature by using two active control actions: the front steering angle and the brake steering force. Bacterial forging optimization algorithm is used to adjust the parameters weights of the proposed controller. Simulation resul
... Show MoreThe electrical performance of bottom-gate/top source-drain contact for p-channel organic field-effect transistors (OFETs) using poly(3-hexylthiophene) (P3HT) as an active semiconductor layer with two different gate dielectric materials, Polyvinylpyrrolidone (PVP) and Hafnium oxide (HfO2), is investigated in this work. The output and transfer characteristics were studied for HfO2, PVP and HfO2/PVP as organic gate insulator layer. Both characteristics show a high drain current at the gate dielectric HfO2/PVP equal to -0.0031A and -0.0015A for output and transfer characteristics respectively, this can be attributed to the increasing of the dielectric capacitance. Transcondactance characteristics also studied for the three organic mater
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