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Area efficient test circuit for library standard cell qualification
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High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction.

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Publication Date
Sun Jan 01 2017
Journal Name
Al-utroha L Sports Scinece
Standard levels for measuring the administrative work of sport unions in the Iraqi national union Olympic Committee
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The sports institutions in general are affected and contact with sport in particular the environmental factor, whether political or economic, which makes them in constant need to consider their administrative applications to increase the confidence of their employees because of their suitability or consistency with the new reality according to the sports activities that relate to it, The stalemate in administrative and technical aspects of the administrative work method in the majority of the Olympic sports federations makes the achievement of most of the goals far from the present reality, and the selection of suitable alternatives to achieve the objectives by those who disagree with the concepts of modern dictatorial standards It leads to

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Publication Date
Tue Aug 03 2021
Journal Name
Journal Of Accounting And Financial Studies ( Jafs )
Enhancing Assurance Services Using Non-Renewable Resources Standard (NR0401) “Constructive Materials: Applied Research for Kufa Cement Factory
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The importance of this study stems from the importance of preserving the environment and creating a clean sustainable environment from waste and emissions and all the operations of industrial companies in general and cement companies in particular by activating sustainability accounting standards. The research aims to identify and diagnose deviations in violation of sustainability standards by employing the non-renewable resources standard (NR0401) For the construction industries to create a sustainable audit environment, the deductive approach was followed in the theoretical side and the inductive and descriptive approach to the practical side. The most important results of the research were the possibility of applying sustainab

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Publication Date
Mon Apr 01 2024
Journal Name
Baghdad Science Journal
Simultaneous spectrophotometric method for determination of both ciprofloxacin and cephalexin by using H-point standard addition method
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طريقة سهلة وبسيطة ودقيقة لتقدير السبروفلوكساسين  في وجود السيفاليكسين او العكس بالعكس في خليط منهما. طبقت الطريقة المقترحة بطريقة الاضافة القياسية لنقطة بنجاح في تقدير السبروفلوكساسين بوجود السيفاليكسين كمتداخل عند الاطوال الموجية 240-272.3 نانوميتر وبتراكيز مختلفة من  السبروفلوكساسين 4-18 مايكروغرام . مل-1 وكذلك تقدير السيفاليكسين بوجود السبروفلوكساسين الذي يتداخل باطوال موجية 262-285.7 نانوميتر وبتراكيز مخ

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Publication Date
Mon May 11 2020
Journal Name
Baghdad Science Journal
DEO: A Dynamic Event Order Strategy for t-way Sequence Covering Array Test Data Generation
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Sequence covering array (SCA) generation is an active research area in recent years. Unlike the sequence-less covering arrays (CA), the order of sequence varies in the test case generation process. This paper reviews the state-of-the-art of the SCA strategies, earlier works reported that finding a minimal size of a test suite is considered as an NP-Hard problem. In addition, most of the existing strategies for SCA generation have a high order of complexity due to the generation of all combinatorial interactions by adopting one-test-at-a-time fashion. Reducing the complexity by adopting one-parameter- at-a-time for SCA generation is a challenging process. In addition, this reduction facilitates the supporting for a higher strength of

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Publication Date
Mon May 11 2020
Journal Name
Baghdad Science Journal
DEO: A Dynamic Event Order Strategy for t-way Sequence Covering Array Test Data Generation
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Sequence covering array (SCA) generation is an active research area in recent years. Unlike the sequence-less covering arrays (CA), the order of sequence varies in the test case generation process. This paper reviews the state-of-the-art of the SCA strategies, earlier works reported that finding a minimal size of a test suite is considered as an NP-Hard problem. In addition, most of the existing strategies for SCA generation have a high order of complexity due to the generation of all combinatorial interactions by adopting one-test-at-a-time fashion. Reducing the complexity by adopting one-parameter- at-a-time for SCA generation is a challenging process. In addition, this reduction facilitates the supporting for a higher strength of cove

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Publication Date
Sun Mar 01 2009
Journal Name
Baghdad Science Journal
Study of ELISA and antibiotic sensitivity test for Salmonella enteritidis as experimental infection in mice
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Salmonella enteritidis one of more important as epidemiological bacteria between other salmonella types. It is very important pathologically that cause food poising and gastrointestinal tract infections. This study includes some of immunological changes that appear by ELISA test and antibiotic sensitivity test against these bacteria in mice. ELISA test results appears high immunological response happen after 3 days of inoculation, mean titration readings beginning 0.198 and the maximum mean titration after 15 days of inoculation 1.538 and begin to decrease after this time slowly to remain about 0.297 after 40 days of inoculation. An antibiotics sensitivity test result appears, this bacteria sensitive to Chloramphenicol, Ceftriaxone,

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Publication Date
Sun Aug 03 2025
Journal Name
Journal Of Physical Education
Specifying Standard Scores and Levels for Some Physical Variables as Indicators for Selecting Youth Soccer Players Aged (17 – 19) years Old
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Publication Date
Fri Dec 20 2019
Journal Name
Iet Circuits, Devices & Systems
Multi‐bit error control coding with limited correction for high‐performance and energy‐efficient network on chip
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In the presence of deep submicron noise, providing reliable and energy‐efficient network on‐chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)‐based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi‐bit error protection while achieving high‐energy savings. This is achieved by calculating two‐dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high‐energy savings are achieved. The res

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Publication Date
Sat May 01 2021
Journal Name
Journal Of Physics: Conference Series
An Efficient Shrinkage Estimators For Generalized Inverse Rayleigh Distribution Based On Bounded And Series Stress-Strength Models
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Abstract<p>In this paper, we investigate two stress-strength models (Bounded and Series) in systems reliability based on Generalized Inverse Rayleigh distribution. To obtain some estimates of shrinkage estimators, Bayesian methods under informative and non-informative assumptions are used. For comparison of the presented methods, Monte Carlo simulations based on the Mean squared Error criteria are applied.</p>
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Publication Date
Tue Jul 01 2014
Journal Name
Ieee Transactions On Circuits And Systems I: Regular Papers
Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip
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Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number o

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