Today in the digital realm, where images constitute the massive resource of the social media base but unfortunately suffer from two issues of size and transmission, compression is the ideal solution. Pixel base techniques are one of the modern spatially optimized modeling techniques of deterministic and probabilistic bases that imply mean, index, and residual. This paper introduces adaptive pixel-based coding techniques for the probabilistic part of a lossy scheme by incorporating the MMSA of the C321 base along with the utilization of the deterministic part losslessly. The tested results achieved higher size reduction performance compared to the traditional pixel-based techniques and the standard JPEG by about 40% and 50%,

In this paper, a compact multiband printed dipole antenna is presented as a candidate for use in wireless communication applications. The proposed fractal antenna design is based on the second level tent transformation. The space-filling property of this fractal geometry permits producing longer lengths in a more compact size. Theoretical performance of this antenna has been calculated using the commercially available software IE3D from Zeland Software Inc. This electromagnetic simulator is based on the method of moments (MoM). The proposed dipole antenna has been found to possess a considerable size reduction compared with the conventional printed or wire dipole antenna designed at the same design frequency and using the same substrate

Companies compete greatly with each other today, so they need to focus on innovation to develop their products and make them competitive. Lean product development is the ideal way to develop product, foster innovation, maximize value, and reduce time. Set-Based Concurrent Engineering (SBCE) is an approved lean product improvement mechanism that builds on the creation of a number of alternative designs at the subsystem level. These designs are simultaneously improved and tested, and the weaker choices are removed gradually until the optimum solution is reached finally. SBCE implementations have been extensively performed in the automotive industry and there are a few case studies in the aerospace industry. This research describe the use o

Choosing antimicrobials is a common dilemma when the expected rate of bacterial resistance is high. The observed resistance values in unequal groups of isolates tested for different antimicrobials can be misleading. This can affect the decision to recommend one antibiotic over the other. We analyzed recalled data with the statistical consideration of unequal sample groups. Data was collected concerning children suspected to have typhoid fever at Al Alwyia Pediatric Teaching Hospital in Baghdad, Iraq. The study period extended from September 2021 to September 2022. A novel algorithm was developed to compare the drug sensitivity among unequal numbers of Salmonella typhi (S. Typhi) isolates tested with different antibacterials.

High vehicular mobility causes frequent changes in the density of vehicles, discontinuity in inter-vehicle communication, and constraints for routing protocols in vehicular ad hoc networks (VANETs). The routing must avoid forwarding packets through segments with low network density and high scale of network disconnections that may result in packet loss, delays, and increased communication overhead in route recovery. Therefore, both traffic and segment status must be considered. This paper presents real-time intersection-based segment aware routing (RTISAR), an intersection-based segment aware algorithm for geographic routing in VANETs. This routing algorithm provides an optimal route for forwarding the data packets toward their destination

In this research a new system identification algorithm is presented for obtaining an optimal set of mathematical models for system with perturbed coefficients, then this algorithm is applied practically by an “On Line System Identification Circuit”, based on real time speed response data of a permanent magnet DC motor. Such set of mathematical models represents the physical plant against all variation which may exist in its parameters, and forms a strong mathematical foundation for stability and performance analysis in control theory problems.

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL).
This HDL program is then used to configure an FPGA to implement the designed circuit.