In this paper, we present a Branch and Bound (B&B) algorithm of scheduling (n) jobs on a single machine to minimize the sum total completion time, total tardiness, total earliness, number of tardy jobs and total late work with unequal release dates. We proposed six heuristic methods for account upper bound. Also to obtain lower bound (LB) to this problem we modified a (LB) select from literature, with (Moore algorithm and Lawler's algorithm).  And some dominance rules were suggested. Also, two special cases were derived. Computational experience showed the proposed (B&B) algorithm was effective in solving problems with up to (16) jobs, also the upper bounds and the lower bound were effective in restr

The necessary optimality conditions with Lagrange multipliers  are studied and derived for a new class that includes the system of Caputo–Katugampola fractional derivatives to the optimal control problems with considering the end time free. The formula for the integral by parts has been proven for the left Caputo–Katugampola fractional derivative that contributes to the finding and deriving the necessary optimality conditions. Also, three special cases are obtained, including the study of the necessary optimality conditions when both the final time  and the final state  are fixed. According to convexity assumptions prove that necessary optimality conditions are sufficient optimality conditions.

Background: Lateral cephalometric radiography is commonly used as a standard tool in orthodontic assessment and treatment planning. This study aimed to determine the tongue and surrounding space area in a sample of Iraqi adults with class I dental and skeletal pattern. Materials and methods: The study included thirty healthy subjects (15 males and 15 females) with an age ranged between 23-34 years and class I dental and skeletal pattern with no history of any sleep related disorders. The assessed cephalometric measurement included length and height of the tongue and position of hyoid bone from cervical line. Descriptive statistics were obtained for the data. Genders difference was evaluated by independent sample t-test. Results: There wer

A modification to cascaded single-stage distributed amplifier (CSSDA) design by using active inductor is proposed. This modification is shown to render the amplifier suitable for high gain operation in small on-chip area. Microwave office program simulation of the Novel design approach shows that it has performance compatible with the conventional distributed amplifiers but with smaller area. The CSSDA is suitable for optical and satellite communication systems.

In this paper, an algorithm is suggested to train a single layer feedforward neural network to function as a heteroassociative memory. This algorithm enhances the ability of the memory to recall the stored patterns when partially described noisy inputs patterns are presented. The algorithm relies on adapting the standard delta rule by introducing new terms, first order term and second order term to it. Results show that the heteroassociative neural network trained with this algorithm perfectly recalls the desired stored pattern when 1.6% and 3.2% special partially described noisy inputs patterns are presented.

Quantum channels enable the achievement of communication tasks inaccessible to their
classical counterparts. The most famous example is the distribution of secret keys. Unfortunately, the rate
of generation of the secret key by direct transmission is fundamentally limited by the distance. This limit
can be overcome by the implementation of a quantum repeater. In order to boost the performance of the
repeater, a quantum repeater based on cut-off with two different types of quantum memories is suggestd,
which reduces the effect of decoherence during the storage of a quantum state.

High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction.