Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
Microfluidic devices provide distinct benefits for developing effective drug assays and screening. The microfluidic platforms may provide a faster and less expensive alternative. Fluids are contained in devices with considerable micrometer-scale dimensions. Owing to this tight restriction, drug assay quantities are minute (milliliters to femtoliters). In this research, a microfluidic chip consisting of micro-channels carved on substrate materials built using an Acrylic (Polymethyl Methacrylate, PMMA) chip was designed using a Carbon Dioxide (CO2) laser machine. The CO2 parameters influence the chip’s width, depth, and roughness. To have a regular channel surface, and low roughness, the laser power (60 W), with scanning speed (250 m/s)
... Show MoreError control schemes became a necessity in network-on-chip (NoC) to improve reliability as the on-chip interconnect errors increase with the continuous shrinking of geometry. Accordingly, many researchers are trying to present multi-bit error correction coding schemes that perform a high error correction capability with the simplest design possible to minimize area and power consumption. A recent work, Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB), showed a huge reduction in area and power consumption compared to a well-known scheme, namely, Hamming product code (HPC) with Type-II HARQ. Moreover, the authors showed that the proposed scheme can correct 11 random errors which is considered a high
... Show MoreNS-2 is a tool to simulate networks and events that occur per packet sequentially based on time and are widely used in the research field. NS-2 comes with NAM (Network Animator) that produces a visual representation it also supports several simulation protocols. The network can be tested end-to-end. This test includes data transmission, delay, jitter, packet-loss ratio and throughput. The Performance Analysis simulates a virtual network and tests for transport layer protocols at the same time with variable data and analyzes simulation results based on the network simulator NS-2.
The aesthetic contents of data visualization is one of the contemporary areas through which data scientists and designers have been able to link data to humans, and even after reaching successful attempts to model data visualization, it wasn't clear how that reveals how it contributed to choosing the aesthetic content as an input to humanize these models, so the goal of the current research is to use The analytical descriptive approach aims to identify the aesthetic contents in data visualization, which the researchers interpreted through pragmatic philosophy and Kantian philosophy, and analyze a sample of data visualization models to reveal the aesthetic entrances in them to explain how to humanize them. The two researchers reached seve
... Show MoreAbstract\
In this research, estimated the reliability of water system network in Baghdad was done. to assess its performance during a specific period. a fault tree through static and dynamic gates was belt and these gates represent logical relationships between the main events in the network and analyzed using dynamic Bayesian networks . As it has been applied Dynamic Bayesian networks estimate reliability by translating dynamic fault tree to Dynamic Bayesian networks and reliability of the system appreciated. As was the potential for the expense of each phase of the network for each gate . Because there are two parts to the Dynamic Bayesian networks and two part of gate (AND), which includes the three basic units of the
... Show MoreComputational study of three-dimensional laminar and turbulent flows around electronic chip (heat source) located on a printed circuit board are presented. Computational field involves the solution of elliptic partial differential equations for conservation of mass, momentum, energy, turbulent energy, and its dissipation rate in finite volume form. The k-ε turbulent model was used with the wall function concept near the walls to treat of turbulence effects. The SIMPLE algorithm was selected in this work. The chip is cooled by an external flow of air. The goals of this investigation are to investigate the heat transfer phenomena of electronic chip located in enclosure and how we arrive to optimum level for cooling of this chip. These par
... Show More