We define L-contraction mapping in the setting of D-metric spaces analogous to L-contraction mappings [1] in complete metric spaces. Also, give a definition for general D- matric spaces.And then prove the existence of fixed point for more general class of mappings in generalized D-metric spaces.
In this study, we present a new steganography method depend on quantizing the perceptual color spaces bands. Four perceptual color spaces are used to test the new method which is HSL, HSV, Lab and Luv, where different algorithms to calculate the last two-color spaces are used. The results reveal the validity of this method as a steganoic method and analysis for the effects of quantization and stegano process on the quality of the cover image and the quality of the perceptual color spaces bands are presented.
In this thesis, we introduced some types of fibrewise topological spaces by using a near soft set, various related results also some fibrewise near separation axiom concepts and a fibrewise soft ideal topological spaces. We introduced preliminary concepts of topological spaces, fibrewise topology, soft set theory and soft ideal theory. We explain and discuss new notion of fibrewise topological spaces, namely fibrewise soft near topological spaces, Also, we show the notions of fibrewise soft near closed topological spaces, fibrewise soft near open topological spaces, fibrewise soft near compact spaces and fibrewise locally soft near compact spaces. On the other hand, we studied fibrewise soft near forms of the more essent
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The aim of this paper is to introduce and study the notion type of fibrewise topological spaces, namely fibrewise fuzzy j-topological spaces, Also, we introduce the concepts of fibrewise j-closed fuzzy topological spaces, fibrewise j-open fuzzy topological spaces, fibrewise locally sliceable fuzzy j-topological spaces and fibrewise locally sectionable fuzzy j-topological spaces. Furthermore, we state and prove several Theorems concerning these concepts, where j = {δ, θ, α, p, s, b, β}.
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It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.
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