This study includes the preparation of the ferrite nanoparticles Cu_xCe_0.3-XNi_0.7Fe₂O₄ (where: x = 0, 0.05, 0.1, 0.15, 0.2, 0.25, 0.3) using the sol-gel (auto combustion) method, and citric acid was used as a fuel for combustion. The results of the tests conducted by X-ray diffraction (XRD), emitting-field scanning electron microscopy (FE-SEM), energy-dispersive X-ray analyzer (EDX), and Vibration Sample Magnetic Device (VSM) showed that the compound has a face-centered cubic structure, and the lattice constant is increased with increasing Cu ion. On the other hand, the compound has apparent porosity and spherical particles, and t

Item Difficulty and Item Discrimination Coefficient for School and College Ability Tests (SCAT) Advanced Form in Classical Test Theory (CTT) and Item Response Theory (IRT) and the Correlation among Them Mohammad moqasqas Haifa T. Albokai Assistant Professor of Measurement and Evaluation Associate Professor of Measurement and Evaluation College of Education, Taibah University The aim of this study was to study the item difficulty and item discrimination of the SCAT (advance form) with CTT, and IRT, and to study the correlation among them. To do this, the researchers used the data of their previous study, which conducted in (2011). It consisted of (3943) subject. Then, they used two-statistical programs (TAP, Bilog-MG-3) to obtain the item

Multiplicative inverse in GF (2 m ) is a complex step in some important application such as Elliptic Curve Cryptography (ECC) and other applications. It operates by multiplying and squaring operation depending on the number of bits (m) in the field GF (2 m ). In this paper, a fast method is suggested to find inversion in GF (2 m ) using FPGA by reducing the number of multiplication operations in the Fermat's Theorem and transferring the squaring into a fast method to find exponentiation to (2 k ). In the proposed algorithm, the multiplicative inverse in GF(2 m ) is achieved by number of multiplications depending on log 2 (m) and each exponentiation is operates in a single clock cycle by generating a reduction matrix for high power of two ex

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.