This research include design and implementation of an Iraqi cities database using spatial data structure for storing data in two or more dimension called k-d tree .The proposed system should allow records to be inserted, deleted and searched by name or coordinate. All the programming of the proposed system written using Delphi ver. 7 and performed on personal computer (Intel core i3).

This paper proposes a collaborative system called Recycle Rewarding System (RRS), and focuses on the aspect of using information communication technology (ICT) as a tool to promote greening. The idea behind RRS is to encourage recycling collectors by paying them for earning points. In doing so, both the industries and individuals reap the economical benefits of such system. Finally, and more importantly, the system intends to achieve a green environment for the Earth. This paper discusses the design and implementation of the RRS, involves: the architectural design, selection of components, and implementation issues. Five modules are used to construct the system, namely: database, data entry, points collecting and recording, points reward

The spread of Coronavirus has forced populations around the globe to adopt strict measures such as lockdown, home quarantine, and home office. Moreover, in the current development of network communications, people can exploit internet and intranet features in many systems that need to be faster, more efficient, and available on time. Furthermore, with the benefits of using internet-of-things (IoT), through which things are generated, gained, discovered, and proposed without interference, the user could receive the last status without exertion and direct contact (i.e., in a contactless manner). These specifications can be used in a transaction system. This paper proposes an electronic transaction system (ETS) as a replacement for the curr

This research  describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc

  The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar &  reference divider in single chip. Therefore our system consists of  a single chip contains (low phase noise PFD, charge pump, prescalar  & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.

In this research, optical communication coding systems are designed and constructed by utilizing Frequency Shift Code (FSC) technique. Calculations of the system quality represented by signal to noise ratio (S/N), Bit Error Rate (BER),and Power budget are done. In FSC system, the data of Nonreturn- to–zero (NRZ ) with bit rate at 190 kb/s was entered into FSC encoder circuit in transmitter unit. This data modulates the laser source HFCT-5205 with wavelength at 1310 nm by Intensity Modulation (IM) method, then this data is transferred through Single Mode (SM) optical fiber. The recovery of the NRZ is achieved using decoder circuit in receiver unit. The calculations of BER and S/N for FSC system a