In the presence of deep submicron noise, providing reliable and energy‐efficient network on‐chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)‐based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi‐bit error protection while achieving high‐energy savings. This is achieved by calculating two‐dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high‐energy savings are achieved. The res
... Show MoreIn this work, the performance of the receiver in a quantum cryptography system based on BB84 protocol is scaled by calculating the Quantum Bit Error Rate (QBER) of the receiver. To apply this performance test, an optical setup was arranged and a circuit was designed and implemented to calculate the QBER. This electronic circuit is used to calculate the number of counts per second generated by the avalanche photodiodes set in the receiver. The calculated counts per second are used to calculate the QBER for the receiver that gives an indication for the performance of the receiver. Minimum QBER, 6%, was obtained with avalanche photodiode excess voltage equals to 2V and laser diode power of 3.16 nW at avalanche photodiode temperature of -10
... Show MoreThe style of Free-form Geometry (FFG) has emerged in contemporary architecture within the last three decades around the world through the progress of digital design tools and the development of constructive materials. FFG is considered as the hard efforts of several contemporary architects to release their products from familiar restrictions to discover new and unfamiliar styles under the perspective of innovation. Many contemporary architects seek to recognize their forms and facilitate dealing with according to specific dimensional rules. The main research problem is the lack of knowledge, in the field of architecture, in previous literature about the formation processes in achievin
Recently, complementary perfect corona domination in graphs was introduced. A dominating set S of a graph G is said to be a complementary perfect corona dominating set (CPCD – set) if each vertex in is either a pendent vertex or a support vertex and has a perfect matching. The minimum cardinality of a complementary perfect corona dominating set is called the complementary perfect corona domination number and is denoted by . In this paper, our parameter hasbeen discussed for power graphs of path and cycle.
The contemporary ideas were characterized by the abundance and diversity of their knowledge, human and conceptual production, the strategy is both a general and a detailed framework covering all design disciplines both inside and outside the field of architecture. From here, many of these terraces emerged from fields outside the field of architecture, but soon moved to form an important nerve within the field of architecture. Hence the need to define a more comprehensive framework for studying one of the concepts that can frame the framework, namely the concept of "Alliteration", and its adoption as an architectural design strategy aimed at giving the resulting form a feature of rhetoric. So the research highlighted the
... Show MoreMicroservice architecture offers many advantages, especially for business applications, due to its flexibility, expandability, and loosely coupled structure for ease of maintenance. However, there are several disadvantages that stem from the features of microservices, such as the fact that microservices are independent in nature can hinder meaningful communication and make data synchronization more challenging. This paper addresses the issues by proposing a containerized microservices in an asynchronous event-driven architecture. This architecture encloses microservices in containers and implements an event manager to keep track of all the events in an event log to reduce errors in the application. Experiment results show a decline in re
... Show MoreThe continuous advancement in the use of the IoT has greatly transformed industries, though at the same time it has made the IoT network vulnerable to highly advanced cybercrimes. There are several limitations with traditional security measures for IoT; the protection of distributed and adaptive IoT systems requires new approaches. This research presents novel threat intelligence for IoT networks based on deep learning, which maintains compliance with IEEE standards. Interweaving artificial intelligence with standardization frameworks is the goal of the study and, thus, improves the identification, protection, and reduction of cyber threats impacting IoT environments. The study is systematic and begins by examining IoT-specific thre
... Show MoreMaintaining and breeding fish in a pond are a crucial task for a large fish breeder. The main issues for fish breeders are pond management such as the production of food for fishes and to maintain the pond water quality. The dynamic or technological system for breeders has been invented and becomes important to get maximum profit return for aquaponic breeders in maintaining fishes. This research presents a developed prototype of a dynamic fish feeder based on fish existence. The dynamic fish feeder is programmed to feed where sensors detected the fish's existence. A microcontroller board NodeMCU ESP8266 is programmed for the developed h
... Show MoreIn this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other err
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