It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.
The study aims to use the European Excellence Model (EFQM) in assessing the institutional performance of the National Center for Administrative Development and Information Technology in order to determine the gap between the actual reality of the performance of the Center and the standards adopted in the model, in order to know the extent to which the Center seeks to achieve excellence in performance to improve the level of services provided and the adoption of methods Modern and contemporary management in the evaluation of its institutional performance.
The problem of the study was the absence of an institutional performance evaluation system at the centre whereby weaknesses (areas of improvement) and st
... Show MoreIncreasing demands on producing environmentally friendly products are becoming a driving force for designing highly active catalysts. Thus, surfaces that efficiently catalyse the nitrogen reduction reactions are greatly sought in moderating air-pollutant emissions. This contribution aims to computationally investigate the hydrodenitrogenation (HDN) networks of pyridine over the γ-Mo2N(111) surface using a density functional theory (DFT) approach. Various adsorption configurations have been considered for the molecularly adsorbed pyridine. Findings indicate that pyridine can be adsorbed via side-on and end-on modes in six geometries in which one adsorption site is revealed to have the lowest adsorption energy (
... Show MoreTo improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors. So, cache coherency protocol is very important in such kinds of system. MSI, MESI, MOSI, MOESI, etc. are the famous protocols to solve cache coherency problem. We have proposed in this research integrating two states of MESI's cache coherence protocol which are Exclusive and Modified, which responds to a request from reading
... Show MoreWe know that the experiments which conducted by latin square in one location or in one period (season), but there are many cases that need to conduct the same experiments in many locations or in many periods (seasons) to study the interaction between the treatments and locations or between the treatments and periods (seasons) .In this research we present an idea for conduct the experiment in several locations and in many period (seasons) by using LSD , it represent acontribution in the area of design and analysis of experiments ,we had written. we had written (theoretically) the general plans, the mathematical models for these experiments, and finding the derivations of EMS for each component (
... Show MoreThe research aimed to identify “The impact of an instructional-learning design based on the brain- compatible model in systemic thinking among first intermediate grade female students in Mathematics”, in the day schools of the second Karkh Educational directorate.In order to achieve the research objective, the following null hypothesis was formulated:There is no statistically significant difference at the significance level (0.05) among the average scores of the experimental group students who will be taught by applying an (instructional- learning) design based to on the brain–compatible model and the average scores of the control group students who will be taught through the traditional method in the systemic thinking test.The resear
... Show MoreIn this study, iron was coupled with copper to form a bimetallic compound through a biosynthetic method, which was then used as a catalyst in the Fenton-like processes for removing direct Blue 15 dye (DB15) from aqueous solution. Characterization techniques were applied on the resultant nanoparticles such as SEM, BET, EDAX, FT-IR, XRD, and zeta potential. Specifically, the rounded and shaped as spherical nanoparticles were found for green synthesized iron/copper nanoparticles (G-Fe/Cu NPs) with the size ranging from 32-59 nm, and the surface area was 4.452 m2/g. The effect of different experimental factors was studied in both batch and continuous experiments. These factors were H2O2 concentration, G-Fe/CuNPs amount, pH, initial DB15
... Show MoreAbstract: The article aimed to formulate an MLX binary ethosome hydrogel for topical delivery to escalate MLX solubility, facilitate dermal permeation, avoid systemic adverse events, and compare the permeation flux and efficacy with the classical type. MLX ethosomes were prepared using the hot method according to the Box–Behnken experimental design. The formulation was implemented according to 16 design formulas with four center points. Independent variables were (soya lecithin, ethanol, and propylene glycol concentrations) and dependent variables (vesicle size, dispersity index, encapsulation efficiency, and zeta potential). The design suggested the optimized formula (MLX−Ethos−OF) with the highest desirability to perform the
... Show MoreIn this paper, a miniaturized 2 × 2 electro-optic plasmonic Mach– Zehnder switch (MZS) based on metal–polymer–silicon hybrid waveguide is presented. Adiabatic tapers are designed to couple the light between the plasmonic phase shifter, implemented in each of the MZS arms, and the 3-dB input/output directional couplers. For 6 µm-long hybrid plasmonic waveguide supported by JRD1 polymer (r33= 390 pm/V), a π-phase shift voltage of 2 V is obtained. The switch is designed for 1550 nm operation wavelength using COMSOL software and characterizes by 2.3 dB insertion loss, 9.9 fJ/bit power consumption, and 640 GHz operation bandwidth