In this paper, a cognitive system based on a nonlinear neural controller and intelligent algorithm that will guide an autonomous mobile robot during continuous path-tracking and navigate over solid obstacles with avoidance was proposed. The goal of the proposed structure is to plan and track the reference path equation for the autonomous mobile robot in the mining environment to avoid the obstacles and reach to the target position by using intelligent optimization algorithms. Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) Algorithms are used to finding the solutions of the mobile robot navigation problems in the mine by searching the optimal paths and finding the reference path equation of the optimal

In this research, the degradation of Dazomet has been studied by using thermal Fenton process and photo-Fenton processes under UV and lights sun. The optimum values of amounts of the Fenton reagents have been determined (0.07g FeSO4 .7H2O, 3.5µl H2O2) at 25 °C and at pH 7 where the degradation percentages of Dazomet were recorded high. It has been found that solar photo Fenton process was more effective in degradation of Dazomet than photo-Fenton under UV-light and thermal Fenton processes, the percentage of degradation of Dazomet by photo-Fenton under sun light are 88% and 100% at 249 nm and 281 nm respectively, while the percentages of degradation for photo-Fenton under UV-light are 87%, 96% and for thermal Fenton are 70% and 66.8% at 2

Authors in this work design efficient neural networks, which are based on the modified Levenberg - Marquardt (LM) training algorithms to solve non-linear fourth - order three -dimensional partial differential equations in the two kinds in the periodic and in the non-periodic - Periodic. Software reliability growth models are essential tools for monitoring and evaluating the evolution of software reliability. Software defect detection events that occur during testing and operation are often treated as counting processes in many current models. However, when working with large software systems, the error detection process should be viewed as a random process with a continuous state space, since the number of faults found during testin

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.