A true random TTL pulse generator was implemented and investigated for quantum key distribution systems. The random TTL signals are generated by low cost components available in the local markets. The TTL signals are obtained by using true random binary sequences based on registering photon arrival time difference registered in coincidence windows between two single – photon detectors. The true random TTL pulse generator performance was tested by using time to digital converters which gives accurate readings for photon arrival time. The proposed true random pulse TTL generator can be used in any quantum -key distribution system for random operation of the transmitters for these systems

A novel fractal design scheme has been introduced in this paper to generate microstrip bandpass filter designs with miniaturized sizes for wireless applications. The presented fractal scheme is based on Minkowski-like prefractal geometry. The space-filling property and self-similarity of this fractal geometry has found to produce reduced size symmetrical structures corresponding to the successive iteration levels. The resulting filter designs are with sizes suitable for use in modern wireless communication systems. The performance of each of the generated bandpass filter structures up to the 2^nd iteration has been analyzed using a method of moments (MoM) based software IE3D, which is widely adopted in microwave research and in

Single-photon detection concept is the most crucial factor that determines the performance of quantum key distribution (QKD) systems. In this paper, a simulator with time domain visualizers and configurable parameters using continuous time simulation approach is presented for modeling and investigating the performance of single-photon detectors operating in Gieger mode at the wavelength of 830 nm. The widely used C30921S silicon avalanche photodiode was modeled in terms of avalanche pulse, the effect of experiment conditions such as excess voltage, temperature and average photon number on the photon detection efficiency, dark count rate and afterpulse probability. This work shows a general repeatable modeling process for significant perform

This paper discusses using H2 and H∞ robust control approaches for designing control systems. These approaches are applied to elementary control system designs, and their respective implementation and pros and cons are introduced. The H∞ control synthesis mainly enforces closed-loop stability, covering some physical constraints and limitations. While noise rejection and disturbance attenuation are more naturally expressed in performance optimization, which can represent the H₂ control synthesis problem. The paper also applies these two methodologies to multi-plant systems to study the stability and performance of the designed controllers. Simulation results show that the H2 controller tracks a desirable cl

This research  describes the design & implementation of frequency synthesizer using single loop Phase lock loop with the following specifications: Frequency range (1.5 – 2.75) GHz,Step size (1 MHz), Switching time 36.4 µs, & phase noise @10 kHz = -92dBc & spurious -100 dBc

  The development in I.C. technology provide the simplicity in the design of frequency synthesizer because it implements the phase frequency detector(PFD) , prescalar &  reference divider in single chip. Therefore our system consists of  a single chip contains (low phase noise PFD, charge pump, prescalar  & reference divider), voltage controlled oscillator , loop filter & reference oscillator. The single chip

Abstract 

This paper presents mechanical and electrical design, and implementation  process of industrial robot, 3-DoF type SCARA (selective compliment assembly robot arm),with two rotations and one translation used for welding applications.The design process also included the controller design which was based on PLC(programmable logic controller) as well as selection of mechanical and electrical components.The challenge was to use the available components in Iraq with reasonable costs. The robot mentioned is fully automated using programmable logic controller PLC(Zelio type SR3-B261BD),with 16inputs and 10 outputs. The PLC was implemented in FBD logic to obtain three different automatic motions with hi

Non uniform channelization is a crucial task in cognitive radio receivers for obtaining separate channels from the digitized wideband input signal at different intervals of time. The two main requirements in the channelizer are reconfigurability and low complexity. In this paper, a reconfigurable architecture based on a combination of Improved Coefficient Decimation Method (ICDM) and Coefficient Interpolation Method (CIM) is proposed. The proposed Hybrid Coefficient Decimation-Interpolation Method (HCDIM) based filter bank (FB) is able to realize the same number of channels realized using (ICDM) but with a maximum decimation factor divided by the interpolation factor (L), which leads to less deterioration in stop band at