The undetected error probability is an important measure to assess the communication reliability provided by any error coding scheme. Two error coding schemes namely, Joint crosstalk avoidance and Triple Error Correction (JTEC) and JTEC with Simultaneous Quadruple Error Detection (JTEC-SQED), provide both crosstalk reduction and multi-bit error correction/detection features. The available undetected error probability model yields an upper bound value which does not give accurate estimation on the reliability provided. This paper presents an improved mathematical model to estimate the undetected error probability of these two joint coding schemes. According to the decoding algorithm the errors are classified into patterns and their decoding result is checked for failures. The probabilities of the failing patterns are used to build the new models. The improved models have less than 1% error
In this paper different channel coding and interleaving schemes in DS/CDMA system over multipath fading channel were used. Two types of serially concatenated coding were presented. The first one composed of Reed-Solomon as outer code, convolutional code as inner code and the interleaver between the outer and inner codes and the second consist of convolutional code as outer code, interleaved in the middle and differential code as an inner code. Bit error rate performance of different schemes in multipath fading channel was analyzed and compared. Rack receiver was used in DS/CDMA receiver to combine multipath components in order to enhance the signal to noise ratio at the receiver.
The presence of different noise sources and continuous increase in crosstalk in the deep submicrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achie
... Show MoreIn the presence of deep submicron noise, providing reliable and energy‐efficient network on‐chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)‐based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi‐bit error protection while achieving high‐energy savings. This is achieved by calculating two‐dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high‐energy savings are achieved. The res
... Show MoreError control schemes became a necessity in network-on-chip (NoC) to improve reliability as the on-chip interconnect errors increase with the continuous shrinking of geometry. Accordingly, many researchers are trying to present multi-bit error correction coding schemes that perform a high error correction capability with the simplest design possible to minimize area and power consumption. A recent work, Multi-bit Error Correcting Coding with Reduced Link Bandwidth (MECCRLB), showed a huge reduction in area and power consumption compared to a well-known scheme, namely, Hamming product code (HPC) with Type-II HARQ. Moreover, the authors showed that the proposed scheme can correct 11 random errors which is considered a high
... Show MoreIn this paper, we present multiple bit error correction coding scheme based on extended Hamming product code combined with type II HARQ using shared resources for on chip interconnect. The shared resources reduce the hardware complexity of the encoder and decoder compared to the existing three stages iterative decoding method for on chip interconnects. The proposed method of decoding achieves 20% and 28% reduction in area and power consumption respectively, with only small increase in decoder delay compared to the existing three stage iterative decoding scheme for multiple bit error correction. The proposed code also achieves excellent improvement in residual flit error rate and up to 58% of total power consumption compared to the other err
... Show MoreIn this paper, the error distribution function is estimated for the single index model by the empirical distribution function and the kernel distribution function. Refined minimum average variance estimation (RMAVE) method is used for estimating single index model. We use simulation experiments to compare the two estimation methods for error distribution function with different sample sizes, the results show that the kernel distribution function is better than the empirical distribution function.
In this paper we introduce several estimators for Binwidth of histogram estimators' .We use simulation technique to compare these estimators .In most cases, the results proved that the rule of thumb estimator is better than other estimators.
<span lang="EN-US">The fundamental of a downlink massive multiple-input multiple-output (MIMO) energy- issue efficiency strategy is known as minimum mean squared error (MMSE) implementation degrades the performance of a downlink massive MIMO energy-efficiency scheme, so some improvements are adding for this precoding scheme to improve its workthat is called our proposal solution as a proposed improved MMSE precoder (PIMP). The energy efficiency (EE) study has also taken into mind drastically lowering radiated power while maintaining high throughput and minimizing interference issues. We further find the tradeoff between spectral efficiency (SE) and EE although they coincide at the beginning but later their interests become con
... Show More