The Decimation in Frequencey Fast Fourier Transform (DIF FFT) is a computationally intensive digital signal processing function widely used in applications such as imaging and wireless communication. Historically, this has been a relatively difficult function to implement optimally in hardware, leading many software designers to use digital signal processors (DSPs) in soft implementations. Unfortunately, because of the funetion's computationally intensive nature, such an approach typically requires multiple DSPs within the system to support the processing requirements. This is costly from a device and board real-estate perspective as well as power intensive

Field-programmable gate array FPGA c-processors have become an extremely cost-effective means of ofl-loading computationally intensive algorichms to improve overall system performance while reducing development time, cost and risks. This paper will describe two DIF FFT implementation approaches, one implemented as an FPGA co-processor and the other using only an external TMS320C641X DSP Family. It will then examine the advantages and disadvantages of these approaches from performance, cost, power consumption and ease of implementation perspectives