Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
The Iraqi-Kuwaiti relations represent a great issue for the Arab-Arab relations. This relation is characterized by specificity for the tension since the foundation of the State of Kuwait until late. There are many factors that prevented the fulfillment of the aspiration towards the development of the relations, perhaps the most important of which is the issue of Mubarak Great Port which is a difficult issue as far as the relation between the two states is concerned. One year after Iraq put the cornerstone of the Great Faw Port. This is considered as the most important hurdle in front of constructing the relations with the neighbor Kuwait
Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number o
... Show MoreUnlike fault diagnosis approaches based on the direct analysis of current and voltage signals, this paper proposes a diagnosis of induction motor faults through monitoring the variations in motor's parameters when it is subjected to an open circuit or short circuit faults. These parameters include stator and rotor resistances, self-inductances, and mutual inductance. The genetic algorithm and the trust-region method are used for the estimation process. Simulation results confirm the efficiency of both the genetic algorithm and the trust-region method in estimating the motor parameters; however, better performance in terms of estimation time is obtained when the trust-region method is adopted. The results also show the po
... Show MoreIn the presence of deep submicron noise, providing reliable and energy‐efficient network on‐chip operation is becoming a challenging objective. In this study, the authors propose a hybrid automatic repeat request (HARQ)‐based coding scheme that simultaneously reduces the crosstalk induced bus delay and provides multi‐bit error protection while achieving high‐energy savings. This is achieved by calculating two‐dimensional parities and duplicating all the bits, which provide single error correction and six errors detection. The error correction reduces the performance degradation caused by retransmissions, which when combined with voltage swing reduction, due to its high error detection, high‐energy savings are achieved. The res
... Show MoreThe design and implementation of an active router architecture that enables flexible network programmability based on so-called "user components" will be presents. This active router is designed to provide maximum flexibility for the development of future network functionality and services. The designed router concentrated mainly on the use of Windows Operating System, enhancing the Active Network Encapsulating Protocol (ANEP). Enhancing ANEP gains a service composition scheme which enables flexible programmability through integration of user components into the router's data path. Also an extended program that creates and then injects data packets into the network stack of the testing machine will be proposed, we will call this program
... Show MoreThis paper presents a fully computerized method to backup the router configuration file. The method consists of a friendly graphical interface programmed by Java programming language.
The proposed method is compared with the two existing methods, namely: TFTP server method and Copy/Paste method. The comparison reveals that the proposed method has many advantages over the existing ones. The proposed method has been implemented on Cisco routers (series 2500, 2600 and 2800).
China's economic policy and its huge capabilities operate according to an expansion strategy, especially in investing foreign projects, as the past ten years have witnessed a major development in the elements of comprehensive strength, especially in the economic field, in 2014 China launched the largest initiative in the world, represented by the Belt and Road Project (BRI), which links nearly 70 countries, through this project, a very important region has emerged, which is (the port of cadres) in Pakistan, as China has headed towards that region and given the highest importance that is in its interest in the first place regardless of the great Pakistani interest, This is consistent with its future aspirations, especially after breaking
... Show MoreSystems on Chips (SoCs) architecture complexity is result of integrating a large numbers of cores in a single chip. The approaches should address the systems particular challenges such as reliability, performance, and power constraints. Monitoring became a necessary part for testing, debugging and performance evaluations of SoCs at run time, as On-chip monitoring is employed to provide environmental information, such as temperature, voltage, and error data. Real-time system validation is done by exploiting the monitoring to determine the proper operation of a system within the designed parameters. The paper explains the common monitoring operations in SoCs, showing the functionality of thermal, voltage and soft error monitors. The different
... Show MoreDynamic Thermal Management (DTM) emerged as a solution to address the reliability challenges with thermal hotspots and unbalanced temperatures. DTM efficiency is highly affected by the accuracy of the temperature information presented to the DTM manager. This work aims to investigate the effect of inaccuracy caused by the deep sub-micron (DSM) noise during the transmission of temperature information to the manager on DTM efficiency. A simulation framework has been developed and results show up to 38% DTM performance degradation and 18% unattended cycles in emergency temperature under DSM noise. The finding highlights the importance of further research in providing reliable on-chip data transmission in DTM application.
The turning process has various factors, which affecting machinability and should be investigated. These are surface roughness, tool life, power consumption, cutting temperature, machining force components, tool wear, and chip thickness ratio. These factors made the process nonlinear and complicated. This work aims to build neural network models to correlate the cutting parameters, namely cutting speed, depth of cut and feed rate, to the machining force and chip thickness ratio. The turning process was performed on high strength aluminum alloy 7075-T6. Three radial basis neural networks are constructed for cutting force, passive force, and feed force. In addition, a radial basis network is constructed to model the chip thickness ratio. T
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